In integrated circuits (ICs), latch up may occur in a four layer pnpn structure. The pnpn structure includes bipolar transistors. Under abnormal conditions, the bipolar transistors can be switched on by a trigger stimulus, such as a positive or negative voltage spike or positive or high negative current-forcing on an input or output pin or power pad of an IC. If the product of the gain of the transistors in the feedback loop is sufficiently large (e.g., b1×b2 is greater than 1) to sustain regeneration, an undesirable current path is created in the pnpn structure. Large amounts of current may be drawn through the pnpn structure, resulting in latch up. For example, large amounts of current may be drawn from the power supply or the I/O pad to ground. Latch up may cause circuit malfunction and/or irreversible damage to the IC.
Conventional techniques for preventing latch up include reducing well and substrate resistances to produce lower voltage drops. Reduced substrate resistance may be achieved with the use of guard rings to surround the wells of the transistors. For example, a heavily doped n-guard ring may surround an n-well and a heavily doped p-guard ring may surround a p-well. Well taps are to connect the well to the guard ring, reducing parasitic resistances. The guard ring have specific latch up design rules which must be met, such as width of the ring, distances of the ring to the I/O pad well tap lengths. These design rules are relatively large and inflexible. The inflexibility of large latch up design rules limits the flexibility for designers in the layout of the IC as well as requiring large chip area to prevent latch up.
The present disclosure is directed to providing flexible and compact latch up design rules.